Memory device, integrated circuit, and manufacturing method of memory device

ABSTRACT

A memory device includes a transistor and a memory cell. The transistor includes a first gate electrode, a second gate electrode, a channel layer, and a gate dielectric layer. The second gate electrode is over the first gate electrode. The channel layer is located between the first gate electrode and the second gate electrode. The gate dielectric layer is located between the channel layer and the second gate electrode. The memory cell is sandwiched between the first gate electrode and the channel layer.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced afast-paced growth. Technological advances in IC materials and designhave produced generations of ICs where each generation has smaller andmore complex circuits than the previous generation. In the course of ICevolution, functional density (i.e., the number of interconnecteddevices per chip area) has generally increased while geometry size(i.e., the smallest component or line that can be created using afabrication process) has decreased. This scaling down process generallyprovides benefits by increasing production efficiency and loweringassociated costs.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIG. 1 is a schematic cross-sectional view of an integrated circuit inaccordance with some embodiments of the disclosure.

FIG. 2A to FIG. 2H are schematic perspective views illustrating variousstages of a manufacturing method of the memory device in FIG. 1.

FIG. 3A to FIG. 3H are cross-sectional views illustrating various stagesof the manufacturing method of the memory device in FIG. 2A to FIG. 2H.

FIG. 4 is a cross-sectional view of a memory device in accordance withsome alternative embodiments of the disclosure.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly.

FIG. 1 is a schematic cross-sectional view of an integrated circuit ICin accordance with some embodiments of the disclosure. In someembodiments, the integrated circuit IC includes a substrate 20, aninterconnect structure 30, a passivation layer 40, a post-passivationlayer 50, a plurality of conductive pads 60, and a plurality ofconductive terminals 70. In some embodiments, the substrate 20 is madeof elemental semiconductor materials, such as crystalline silicon,diamond, or germanium; compound semiconductor materials, such as siliconcarbide, gallium arsenic, indium arsenide, or indium phosphide; or alloysemiconductor materials, such as silicon germanium, silicon germaniumcarbide, gallium arsenic phosphide, or gallium indium phosphide. Thesubstrate 20 may be a bulk silicon substrate, a silicon-on-insulator(SOI) substrate, or a germanium-on-insulator (GOI) substrate.

In some embodiments, the substrate 20 includes various doped regionsdepending on circuit requirements (e.g., p-type semiconductor substrateor n-type semiconductor substrate). In some embodiments, the dopedregions are doped with p-type or n-type dopants. For example, the dopedregions may be doped with p-type dopants, such as boron or BF₂; n-typedopants, such as phosphorus or arsenic; and/or combinations thereof. Insome embodiments, these doped regions serve as source/drain regions of afirst transistor T1, which is over the substrate 20. Depending on thetypes of the dopants in the doped regions, the first transistor T1 maybe referred to as n-type transistor or p-type transistor. In someembodiments, the first transistor T1 further includes a metal gate and achannel under the metal gate. The channel is located between the sourceregion and the drain region to serve as a path for electron to travelwhen the first transistor T1 is turned on. On the other hand, the metalgate is located above the substrate 20 and is embedded in theinterconnect structure 30. In some embodiments, the first transistor T1is formed using suitable Front-end-of-line (FEOL) process. Forsimplicity, one first transistor T1 is shown in FIG. 1. However, itshould be understood that more than one first transistors T1 may bepresented depending on the application of the integrated circuit IC.When multiple first transistors T1 are presented, these firsttransistors T1 may be separated by shallow trench isolation (STI; notshown) located between two adjacent first transistors T1.

As illustrated in FIG. 1, the interconnect structure 30 is disposed onthe substrate 20. In some embodiments, the interconnect structure 30includes a plurality of conductive vias 32, a plurality of conductivepatterns 34, a plurality of dielectric layers 36, and a plurality ofmemory devices MD. As illustrated in FIG. 1, the conductive patterns 34and the conductive vias 32 are embedded in the dielectric layers 36. Insome embodiments, the conductive patterns 34 located at different levelheights are connected to one another through the conductive vias 32. Inother words, the conductive patterns 34 are electrically connected toone another through the conductive vias 32. In some embodiments, thebottommost conductive vias 32 are connected to the first transistor T1.For example, the bottommost conductive vias 32 are connected to themetal gate, which is embedded in the bottommost dielectric layer 36, ofthe first transistor T1. In other words, the bottommost conductive vias32 establish electrical connection between the first transistor T1 andthe conductive patterns 34 of the interconnect structure 30. Asillustrated in FIG. 1, the bottommost conductive via 32 is connected tothe metal gate of the first transistor T1. It should be noted that insome alternative cross-sectional views, other bottommost conductive vias32 are also connected to source/drain regions of the first transistorT1. That is, in some embodiments, the bottommost conductive vias 32 maybe referred to as “contact structures” of the first transistor T1.

In some embodiments, a material of the dielectric layers 36 includespolyimide, epoxy resin, acrylic resin, phenol resin, benzocyclobutene(BCB), polybenzooxazole (PBO), or any other suitable polymer-baseddielectric material. Alternatively, the dielectric layers 36 may beformed of oxides or nitrides, such as silicon oxide, silicon nitride, orthe like. The dielectric layers 36 may be formed by suitable fabricationtechniques such as spin-on coating, chemical vapor deposition (CVD),plasma-enhanced chemical vapor deposition (PECVD), or the like.

In some embodiments, a material of the conductive patterns 34 and theconductive vias 32 includes aluminum, titanium, copper, nickel,tungsten, or alloys thereof. The conductive patterns 34 and theconductive vias 32 may be formed by electroplating, deposition, and/orphotolithography and etching. In some embodiments, the conductivepatterns 34 and the underlying conductive vias 32 are formedsimultaneously. It should be noted that the number of the dielectriclayers 36, the number of the conductive patterns 34, and the number ofthe conductive vias 32 illustrated in FIG. 1 are merely for illustrativepurposes, and the disclosure is not limited thereto. In some alternativeembodiments, fewer or more layers of the dielectric layers 36, theconductive patterns 34, and/or the conductive vias 32 may be formeddepending on the circuit design.

In some embodiments, the memory devices MD are also embedded in theinterconnect structure 30. For example, each memory device MD isembedded in one of the dielectric layers 36. The formation method andthe structure of the memory devices MD will be described in detaillater. Depending on the types of the memory cells in the memory devicesMD, the memory devices MD may be Silicon-Oxide-Nitride-Oxide-Silicon(SONOS) devices, Ferroelectric Random Access Memory (FeRAM) devices,Resistive Random Access Memory (RRAM) devices, Dynamic Random AccessMemory (DRAM) device, Static Random Access Memory (SRAM) device,Magnetoresistive Random Access Memory (MRAM), or the like.

As illustrated in FIG. 1, the passivation layer 40, the conductive pads60, the post-passivation layer 50, and the conductive terminals 70 aresequentially formed on the interconnect structure 30. In someembodiments, the passivation layer 40 is disposed on the topmostdielectric layer 36 and the topmost conductive patterns 34. In someembodiments, the passivation layer 40 has a plurality of openingspartially exposing each topmost conductive pattern 34. In someembodiments, the passivation layer 40 is a silicon oxide layer, asilicon nitride layer, a silicon oxy-nitride layer, or a dielectriclayer formed by other suitable dielectric materials. The passivationlayer 40 may be formed by suitable fabrication techniques such asHDP-CVD, PECVD, or the like.

In some embodiments, the conductive pads 60 are formed over thepassivation layer 40. In some embodiments, the conductive pads 60 extendinto the openings of the passivation layer 40 to be in direct contactwith the topmost conductive patterns 34. That is, the conductive pads 60are electrically connected to the interconnect structure 30. In someembodiments, the conductive pads 60 include aluminum pads, copper pads,titanium pads, nickel pads, tungsten pads, or other suitable metal pads.The conductive pads 60 may be formed by, for example, electroplating,deposition, and/or photolithography and etching. It should be noted thatthe number and the shape of the conductive pads 60 illustrated in FIG. 1are merely for illustrative purposes, and the disclosure is not limitedthereto. In some alternative embodiments, the number and the shape ofthe conductive pad 60 may be adjusted based on demand.

In some embodiments, the post-passivation layer 50 is formed over thepassivation layer 40 and the conductive pads 60. In some embodiments,the post-passivation layer 50 is formed on the conductive pads 60 toprotect the conductive pads 60. In some embodiments, thepost-passivation layer 50 has a plurality of contact openings partiallyexposing each conductive pad 60. The post-passivation layer 50 may be apolyimide layer, a PBO layer, or a dielectric layer formed by othersuitable polymers. In some embodiments, the post-passivation layer 50 isformed by suitable fabrication techniques such as HDP-CVD, PECVD, or thelike.

As illustrated in FIG. 1, the conductive terminals 70 are formed overthe post-passivation layer 50 and the conductive pads 60. In someembodiments, the conductive terminals 70 extend into the contactopenings of the post-passivation layer 50 to be in direct contact withthe corresponding conductive pad 60. That is, the conductive terminals70 are electrically connected to the interconnect structure 30 throughthe conductive pads 60. In some embodiments, the conductive terminals 70are conductive pillars, conductive posts, conductive balls, conductivebumps, or the like. In some embodiments, a material of the conductiveterminals 70 includes a variety of metals, metal alloys, or metals andmixture of other materials. For example, the conductive terminals 70 maybe made of aluminum, titanium, copper, nickel, tungsten, tin, and/oralloys thereof. The conductive terminals 70 are formed by, for example,deposition, electroplating, screen printing, or other suitable methods.In some embodiments, the conductive terminals 70 are used to establishelectrical connection with other components (not shown) subsequentlyformed or provided.

As mentioned above, the memory devices MD are embedded in theinterconnect structure 30. Taking the topmost memory device MD shown inFIG. 1 as an example, the formation method and the structure of thismemory device MD will be described below in conjunction with FIG. 2A toFIG. 2H and FIG. 3A to FIG. 3H.

FIG. 2A to FIG. 2H are schematic perspective views illustrating variousstages of a manufacturing method of the memory device MD in FIG. 1. FIG.3A to FIG. 3H are cross-sectional views illustrating various stages ofthe manufacturing method of the memory device MD in FIG. 2A to FIG. 2H.It should be noted that the cross-sectional views of FIG. 3A to FIG. 3Hare taken along cross-sectional line A-A′ in FIG. 2A to FIG. 2H.

Referring to FIG. 2A and FIG. 3A, a dielectric layer 100 is provided. Insome embodiments, the dielectric layer 100 is one of the dielectriclayers 36 of the interconnect structure 30 of FIG. 1, so the detaileddescription thereof is omitted herein.

Referring to FIG. 2B and FIG. 3B, a first gate electrode 200 is formedon the dielectric layer 100. In some embodiments, the first gateelectrode 200 is formed by a photolithography and etching process. Forexample, a metallic material (not shown) is conformally formed on thedielectric layer 100. In some embodiments, the metallic material isdeposited through atomic layer deposition (ALD), CVD, physical vapordeposition (PVD), or the like. Thereafter, a patterned photoresist layer(not shown) is formed on the metallic material to define the shape ofthe subsequently formed first gate electrode 200. Subsequently, anetching process is performed to remove the metallic material that is notcovered by the patterned photoresist layer. The etching processincludes, for example, an anisotropic etching process such as dry etchor an isotropic etching process such as wet etch. Then, the patternedphotoresist layer is removed through a stripping process or the like toexpose the remaining metallic material, which constitutes the first gateelectrode 200.

In some embodiments, the metallic material of the first gate electrode200 includes copper, titanium, tantalum, tungsten, aluminum, zirconium,hafnium, cobalt, titanium aluminum, tantalum aluminum, tungstenaluminum, zirconium aluminum, hafnium aluminum, any other suitablemetal-containing material, or a combination thereof. In someembodiments, the first gate electrode 200 also includes materials tofine-tune the corresponding work function. For example, the metallicmaterial of the first gate electrode 200 may include p-type workfunction materials such as Ru, Mo, WN, ZrSi₂, MoSi₂, TaSi₂, NiSi₂, orcombinations thereof, or n-type work function materials such as Ag,TaCN, Mn, or combinations thereof.

In some embodiments, a barrier layer (not shown) is optionally formedbetween the first gate electrode 200 and the dielectric layer 100, so asto avoid diffusion of atoms between elements. In some embodiments, amaterial of the barrier layer includes titanium nitride (TiN), tantalumnitride (TaN), titanium silicon nitride (TiSiN), tantalum siliconnitride (TaSiN), tungsten silicon nitride (WSiN), titanium carbide(TiC), tantalum carbide (TaC), titanium aluminum carbide (TiAlC),tantalum aluminum carbide (TaAlC), titanium aluminum nitride (TiAlN),tantalum aluminum nitride (TaAlN), or a combination thereof.

In some embodiments, a thickness of the first gate electrode 200 rangesfrom about 30 Å to about 250 Å. In some embodiments, the first gateelectrode 200 has a first portion 200 a and a second portion 200 bconnected to the first portion 200 a. As illustrated in FIG. 2B, thefirst portion 200 a of the first gate electrode 200 extends along afirst direction D1. Meanwhile, the second portion 200 b of the firstgate electrode 200 extends along a second direction D2 perpendicular tothe first direction D1. In other words, the first portion 200 a of thefirst gate electrode 200 is perpendicular to the second portion 200 b ofthe first gate electrode 200. For example, as illustrated in FIG. 2B,the first gate electrode 200 exhibits a T shape from the top view.

Referring to FIG. 2C and FIG. 3C, a memory cell 300 is conformallyformed over the dielectric layer 100 and the first gate electrode 200.For example, the memory cell 300 is formed to be in physical contactwith the dielectric layer 100 and the first gate electrode 200. In someembodiments, the memory cell 300 is a multi-layered structure. Forexample, the memory cell 300 includes a barrier layer 302, a trappinglayer 304, and a tunneling layer 306 stacked in sequential order overthe dielectric layer 100 and the first gate electrode 200.

In some embodiments, the barrier layer 302 is conformally formed on thedielectric layer 100 and the first gate electrode 200. For example, thebarrier layer 302 is in physical contact with the dielectric layer 100and the first gate electrode 200. In some embodiments, the barrier layer302 is formed by a suitable deposition process, such as CVD, PECVD,flowable chemical vapor deposition (FCVD), high-density-plasma chemicalvapor deposition (HDP-CVD), sub-atmospheric chemical vapor deposition(SACVD), PVD, or ALD. In some embodiments, the barrier layer 302 isformed to have a thickness ranging from about 10 Å to about 60 Å. Insome embodiments, a material of the barrier layer 302 includes aluminumoxide (AlO_(x)), silicon oxide (SiO_(x)), or the like.

As illustrated in FIG. 2C and FIG. 3C, the trapping layer 304 isconformally formed on the barrier layer 302. For example, the trappinglayer 304 is in physical contact with the barrier layer 302. In someembodiments, the trapping layer 304 is formed by a suitable depositionprocess, such as CVD, PECVD, FCVD, HDP-CVD, SACVD, PVD, or ALD. In someembodiments, the trapping layer 304 is formed to have a thicknessranging from about 10 Å to about 60 Å. In some embodiments, a materialof the trapping layer 304 is different from the material of the barrierlayer 302. For example, the material of the trapping layer 304 includeshafnium oxide (HfO_(x)), silicon nitride (SiN_(x)), or the like. In someembodiments, the trapping layer 304 is utilized to trap electrons. Forexample, the trapping layer 304 may be utilized to store data. As such,in some embodiments, the trapping layer 304 is referred to as a “storagelayer.”

In some embodiments, the tunneling layer 306 is conformally formed onthe trapping layer 304. For example, the tunneling layer 306 is inphysical contact with the trapping layer 304 such that the trappinglayer 304 is sandwiched between the barrier layer 302 and the tunnelinglayer 306. In some embodiments, the tunneling layer 306 is formed by asuitable deposition process, such as CVD, PECVD, FCVD, HDP-CVD, SACVD,PVD, or ALD. In some embodiments, the tunneling layer 306 is formed tohave a thickness smaller than both of the thickness of the barrier layer302 and the thickness of the trapping layer 304. For example, thethickness of the tunneling layer 306 ranges from about 10 Å to about 30Å. In some embodiments, a material of the tunneling layer 306 includesaluminum oxide (AlO_(x)), silicon oxide (SiO_(x)), or the like. That is,the material of the tunneling layer 306 is the same as the material ofthe barrier layer 302 while being different from the material of thetrapping layer 304. However, the disclosure is not limited thereto. Insome alternative embodiments, the material of the tunneling layer 306may be different from the material of the barrier layer 302. Forexample, the material of the barrier layer 302 may be aluminum oxidewhile the material of the tunneling layer 306 may be silicon oxide.

Depending on the material utilized, the memory cell 300 may be referredto as a “SONOS memory cell” in some embodiments. In some embodiments,the memory cell 300 is further referred to as a “floating gate memorycell.”

Referring to FIG. 2D and FIG. 3D, a channel layer 400 is formed over thefirst gate electrode 200 and the memory cell 300. For example, thechannel layer 400 is disposed on the tunneling layer 306 of the memorycell 300. In some embodiments, the channel layer 400 is in physicalcontact with the tunneling layer 306. In some embodiments, the channellayer 400 partially covers the memory cell 300. For example, at least aportion of the tunneling layer 306 of the memory cell 300 is exposed bythe channel layer 400. In some embodiments, the channel layer 400partially overlaps with the first gate electrode 200 underneath thememory cell 300. For example, as illustrated in FIG. 2D, the channellayer 400 overlaps with a portion of the second portion 200 b of thefirst gate electrode 200 from the top view. In some embodiments, atleast a portion of the memory cell 300 is sandwiched between the firstgate electrode 200 and the channel layer 400.

In some embodiments, the channel layer 400 includes oxide semiconductormaterials, 2D materials, or a combination thereof. Examples of the oxidesemiconductor material include ZnO, IGZO, the like, or a combinationthereof. On the other hand, examples of the 2D materials include MoS₂,WS₂, WSe₂, InSe, the like, or a combination thereof. In someembodiments, the channel layer 400 is made of a single layer having oneof the foregoing materials. However, the disclosure is not limitedthereto. In some alternative embodiments, the channel layer 400 may bemade of a laminate structure of at least two of the foregoing materials.In some embodiments, the channel layer 400 is doped with a dopant toachieve extra stability. For example, the channel layer 400 may be dopedwith silicon dopant or the like. In some embodiments, the channel layer400 is deposited by suitable techniques, such as CVD, ALD, PVD, PECVD,epitaxial growth, or the like.

In some embodiments, the channel layer 400 has a thickness ranging fromabout 7 A to about 10 Å. As illustrated in FIG. 2D, the channel layer400 extends along the first direction D1. In other words, the channellayer 400 is parallel to the first portion 200 a of the first gateelectrode 200. Meanwhile, the channel layer 400 is perpendicular to thesecond portion 200 b of the first gate electrode 200.

Referring to FIG. 2E and FIG. 3E, source/drain regions 500 are formed onthe channel layer 400 and the memory cell 300. For example, thesource/drain regions 500 are formed near two ends of the channel layer400 and extends from the channel layer 400 to the memory cell 300. Thatis, the source/drain regions 500 cover the two tails of the channellayer 400 to be in physical contact with the channel layer 400 and thememory cell 300. For example, the source/drain regions 500 extends fromthe two tails of the channel layer 400 to the tunneling layer 306 of thememory cell 300. In some embodiments, a material of the source/drainregions 500 includes cobalt, tungsten, copper, titanium, tantalum,aluminum, zirconium, hafnium, a combination thereof, or other suitablemetallic materials. In some embodiments, the source/drain regions 500are formed through CVD, ALD, plating, or other suitable depositiontechniques.

In some embodiments, the source/drain regions 500 are formed to have athickness ranging from about 10 Å to about 100 Å. As illustrated in FIG.2E, the source/drain regions 500 respectively exhibits a funnel shapefrom the top view. Moreover, the source/drain regions 500 respectivelyextend along the first direction D1. In some embodiments, thesource/drain regions 500 partially overlap with the first gate electrode200 underneath the memory cell 300 and the channel layer 400. Forexample, as illustrated in FIG. 2E, the source/drain regions 500 overlapwith a portion of the second portion 200 b of the first gate electrode200 from the top view.

Referring to FIG. 2F and FIG. 3F, a gate dielectric layer 600 isconformally formed on the memory cell 300, the channel layer 400, andthe source/drain regions 500. In some embodiments, the gate dielectriclayer 600 is in physical contact with the channel layer 400, thesource/drain regions 500, and the tunneling layer 306 of the memory cell300. As illustrated in FIG. 2F and FIG. 3F, a portion of thesource/drain regions 500 is located between the channel layer 400 andthe gate dielectric layer 600, and another portion of the source/drainregions 500 is located between the tunneling layer 306 of the memorycell 300 and the gate dielectric layer 600. In some embodiments, thegate dielectric layer 600 has a thickness ranging from about 10 Å toabout 100 Å.

In some embodiments, the gate dielectric layer 600 includes siliconoxide, silicon nitride, silicon oxynitride, high-k dielectrics, or acombination thereof. It should be noted that the high-k dielectricmaterials are generally dielectric materials having a dielectricconstant higher than 4, greater than about 12, greater than about 16, oreven greater than about 20. In some embodiments, the gate dielectriclayer 600 includes metal oxides, metal nitrides, metal silicates,transition metal-oxides, transition metal-nitrides, transitionmetal-silicates, oxynitrides of metals, metal aluminates, orcombinations thereof. For example, the gate dielectric layer 600includes hafnium oxide (HfO₂), hafnium silicon oxide (HfSiO), hafniumsilicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafniumtitanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconiumsilicate, zirconium aluminate, silicon nitride, silicon oxynitride,zirconium oxide, titanium oxide, aluminum oxide (Al₂O₃), hafniumdioxide-alumina (HfO₂—Al₂O₃) alloy, and/or combinations thereof. Theforegoing materials may be deposited by suitable fabrication techniquessuch as ALD, CVD, metalorganic CVD (MOCVD), PVD, thermal oxidation,UV-ozone oxidation, remote plasma atomic layer deposition (RPALD),plasma-enhanced atomic layer deposition (PEALD), molecular beamdeposition (MBD), or combinations thereof. However, the disclosure isnot limited thereto. In some alternative embodiments, a material of thegate dielectric layer 600 includes hexagonal boron nitride (hBN). Whenthe gate dielectric layer 600 includes hBN, the gate dielectric layer600 is formed by the following steps. First, a copper film (not shown)is provided. Thereafter, an hBN film is formed on the copper film. Insome embodiments, the hBN film is deposited through CVD, low-pressurechemical vapor deposition (LPCVD), or other suitable deposition methods.In some embodiments, the precursors (for example, the process gases) forforming the hBN film include ammonia borane (H₃NBH₃), borazine (B₃H₆N₃),a combination thereof, and/or the like. In some embodiments, thetemperature of the precursors is in the range from about 60° C. to about130° C. In some embodiments, during the deposition of the hBN film, theexposed copper atoms of the copper film act as a catalyst to activatethe precursor molecules (i.e. boron and nitride), so the boron nitridemonolayer to be grown on the copper film. After the formation of the hBNfilm, the hBN film may be peeled off from the copper film andtransferred onto the memory cell 300, the channel layer 400, and thesource/drain regions 500 to serve as the gate dielectric layer 600.

Referring to FIG. 2G and FIG. 3G, a second gate electrode 700 is formedon the gate dielectric layer 600. For example, the second gate electrode700 is formed such that the gate dielectric layer 600 is sandwichedbetween the channel layer 400 and the second gate electrode 700. In someembodiments, the formation method of the second gate electrode 700 issimilar to that of the first gate electrode 200, so the detaileddescription thereof is omitted herein. In some embodiments, a materialof the second gate electrode 700 is the same as the material of thefirst gate electrode 200. However, the disclosure is not limitedthereto. In some alternative embodiments, the material of the secondgate electrode 700 is different from the material of the first gateelectrode 200. In some embodiments, the material of the second gateelectrode 700 includes copper, titanium, tantalum, tungsten, aluminum,zirconium, hafnium, cobalt, titanium aluminum, tantalum aluminum,tungsten aluminum, zirconium aluminum, hafnium aluminum, any othersuitable metal-containing material, or a combination thereof. In someembodiments, the second gate electrode 700 also includes materials tofine-tune the corresponding work function. For example, the material ofthe second gate electrode 700 may include p-type work function materialssuch as Ru, Mo, WN, ZrSi₂, MoSi₂, TaSi₂, NiSi₂, or combinations thereof,or n-type work function materials such as Ag, TaCN, Mn, or combinationsthereof.

In some embodiments, a thickness of the second gate electrode 700 rangesfrom about 10 Å to about 1000 Å. In some embodiments, the second gateelectrode 700 has a first portion 700 a and a second portion 700 bconnected to the first portion 700 a. As illustrated in FIG. 2G, thefirst portion 700 a of the second gate electrode 700 extends along thesecond direction D2. Meanwhile, the second portion 700 b of the secondgate electrode 700 extends along the first direction D1. In other words,the first portion 700 a of the second gate electrode 700 isperpendicular to the second portion 700 b of the second gate electrode700. For example, as illustrated in FIG. 2G, the second gate electrode700 exhibits a funnel shape or a T shape from the top view. In someembodiments, the second gate electrode 700 is partially overlapped withthe source/drain regions 500, the channel layer 400, the memory cell300, and the first gate electrode 200, as shown in FIG. 2G and FIG. 3G.That is, a portion of the memory cell 300, a portion of the channellayer 400, a portion of the source/drain regions 500, and a portion ofthe gate dielectric layer 600 are located between the first gateelectrode 200 and the second gate electrode 700.

Referring to FIG. 2H and FIG. 3H, source/drain contacts 800 and a gatecontact 900 are formed on the gate dielectric layer 600 to obtain amemory device MD. In some embodiments, the source/drain contacts 800 areformed by the following steps. First, openings OP are formed in the gatedielectric layer 600 to expose at least a portion of the source/drainregions 500. For example, the openings OP of the gate dielectric layer600 expose two ends of the source/drain regions 500. After the openingsOP are formed, a metallic material is filled into the openings OP, so asto form the source/drain contacts 800. In some embodiments, a materialof the source/drain contacts 800 is the same as the material of thesource/drain regions 500. However, the disclosure is not limitedthereto. In some alternative embodiments, the material of thesource/drain contacts 800 may be different from the material of thesource/drain regions 500. In some embodiments, the material of thesource/drain contacts 800 includes cobalt, tungsten, copper, titanium,tantalum, aluminum, zirconium, hafnium, a combination thereof, or othersuitable metallic materials. In some embodiments, the metallic materialof the source/drain contacts 800 is formed through CVD, ALD, plating, orother suitable deposition techniques. As illustrated in FIG. 3H, thesource/drain contacts 800 extend into the openings OP of the gatedielectric layer 600 to be in physical contact with the source/drainregions 500. In other words, the source/drain contacts 800 areelectrically connected to the source/drain regions 500 to serve ascontact plugs for transmitting signal between the source/drain regions500 and other components.

In some embodiments, the gate contact 900 is also formed on the gatedielectric layer 600. The material and the formation method of the gatecontact 900 are similar to that of the source/drain contacts 800, so thedetailed descriptions thereof are omitted herein. In some embodiments,an opening (not shown) is formed to penetrate through the gatedielectric layer 600 and the memory cell 300 to partially expose thefirst gate electrode 200. The gate contact 900 extends into this openingto be in physical contact with the first gate electrode 200. In otherwords, the gate contact 900 is electrically connected to the first gateelectrode 200 to serve as a contact plug for transmitting signal betweenthe first gate electrode 200 and other components. For example, thefirst gate electrode 200 is connected to a ground voltage through thegate contact 900. In some embodiments, the ground voltage may be areference voltage and remains a constant. In some embodiments, the firstgate electrode 200 and the second gate electrode 700 are electricallyinsulated. For example, as illustrated in FIG. 2H, the second gateelectrode 700 is spaced apart from the gate contact 900, so as to beelectrically insulated from the gate contact 900. In some embodiments,the second gate electrode 700 is connected to a voltage different fromthe ground voltage in which the first gate electrode 200 is connectedto. That is, different biases are applied to the first gate electrode200 and the second gate electrode 700 during operation of the memorydevice MD. For example, the second gate electrode 700 may be connectedto a voltage higher than the ground voltage. However, the disclosure isnot limited thereto. In some alternative embodiments, the second gateelectrode 700 may be connected to a voltage lower than the groundvoltage.

In some embodiments, the source/drain contacts 800 and the gate contact900 are respectively formed to have a thickness ranging from about 10 Åto about 1000 Å. In some embodiments, the source/drain contacts 800 andthe gate contact 900 are simultaneously formed. That is, thesource/drain contact 800 and the gate contact 900 belong to the samelayer and are formed by the same process. It should be noted thatalthough FIGS. 2G-2H and FIGS. 3G-3H illustrated that the formation ofthe second gate electrode 700 precedes the formation of the source/draincontacts 800 and the gate contact 900, the disclosure is not limitedthereto. In some alternative embodiments, the second gate electrode 700,the source/drain contacts 800, and the gate contact 900 may besimultaneously formed through the same process. As illustrated in FIG.3H, top surfaces of the source/drain contacts 800 and a top surface ofthe second gate electrode 700 are substantially levelled (i.e. locatedat the same level height). However, the disclosure is not limitedthereto. In some alternative embodiments, the top surfaces of thesource/drain contacts 800 may be located at a level height higher thanor lower than that of the top surface of the second gate electrode 700.

After the formation of the source/drain contacts 800 and the gatecontact 900, the process of manufacturing the memory device MD issubstantially completed. In some embodiments, the first gate electrode200, the channel layer 400, the source/drain regions 500, the gatedielectric layer 600, the second gate electrode 700, the source/draincontacts 800, and the gate contact 900 are collectively referred to as asecond transistor T2. In other words, the memory device MD includes thesecond transistor T2 and the memory cell 300, and the memory cell 300 isembedded/integrated within the second transistor T2. In someembodiments, the first gate electrode 200 of the second transistor T2serves as a bottom electrode of the memory cell 300 while the secondgate electrode 700 of the second transistor T2 serves as a top electrodeof the memory cell 300.

In some embodiments, the second transistor T2 is a thin film transistors(TFT). Since the second transistor T2 includes the first gate electrode200 and the second gate electrode 700, the second transistor T2 may bereferred to as a “double gate transistor” or a “dual gate transistor” insome embodiments. Referring to FIG. 1 and FIG. 3H, the source/draincontacts 800 extend from the channel layer 400 to the conductive pads 34of the interconnect structure 30. In other words, the second transistorsT2 is electrically connected to the first transistor T1 and theconductive terminals 80 through the conductive vias 32 and theconductive patterns 34 of the interconnect structure 30. In someembodiments, the second transistors T2 is a selector for the memorydevice MD.

Furthermore, as mentioned above, the memory device MD is embedded in theinterconnect structure 30, which is being considered as formed duringback-end-of-line (BEOL) process. That is, the second transistor T2 andthe memory cell 300 are both being considered as formed during BEOLprocess. However, the disclosure is not limited thereto. In somealternative embodiments, the memory device MD may be formed in thefront-end-of-line (FEOL) process. When the memory device MD is formed inthe front-end-of-line (FEOL) process, the substrate 20 in FIG. 1 may bea SOI substrate and the dielectric layer 100 in FIG. 2A and FIG. 3A maybe the dielectric of the SOI substrate.

As illustrated in FIG. 3H, the channel layer 400 and the source/drainregions 500 are located between the memory cell 300 and the second gateelectrode 700. That is, the second gate electrode 700 and the memorycell 300 are located on opposite sides of the channel layer 400. Assuch, when applying a bias to the second gate electrode 700 to turn onthe second transistor T2 (i.e. driving the electrons to pass through thechannel layer 400), the electric field generated would be far away fromthe storage layer (i.e. the trapping layer 304) of the memory cell 300.As such, the charges stored in the storage layer would not be affectedby the electric field generated from applying the bias, therebyenhancing the read disturbance immunity. In other words, the stabilityof the storage capability of the memory cell 300 may be enhanced, andthe cycle time of the memory device MD may be extended. Moreover, asillustrated in FIG. 3H, the channel layer 400 is located between thesource/drain regions 500 and the memory cell 300, and the source/drainregions 500 are overlapped with the first gate electrode 200. As such,the charges stored in the trapping layer 304 of the memory cell 300 caninteract/affect the electrons/charges in the channel layer 400, therebyallowing the on-resistance (R_(ON)) of the second transistor T2 to betunable based on the charges stored in the trapping layer 304 and thepulse given to the first gate electrode 200. Since the conductance ofthe memory device MD is inversely proportional to R_(ON), by modulatingR_(ON) of the second transistor T2, the conductance of the memory deviceMD may be adjusted, thereby achieving higher flexibility in the memorydevice MD.

FIG. 4 is a cross-sectional view of a memory device MD′ in accordancewith some alternative embodiments of the disclosure. Referring to FIG.4, the memory device MD′ in FIG. 4 is similar to the memory device MD inFIG. 3H, so similar elements are denoted by the same reference numeraland the detailed description thereof is omitted herein. However, in thememory device MD′ of FIG. 4, the memory cell 300′ is a single-layeredstructure. For example, the memory cell 300′ is formed by a singleferroelectric layer. In some embodiments, the ferroelectric layerincludes Pb₃Ge₃O₁₁ (PGO), lead zirconate titanate (PZT), SrBi₂Ta₂O₉(SBTO), SrB₄O₇ (SBO), Sr_(a)Bi_(b)Ta_(c)Nb_(d)O_(x) (SBTN), SrTiO₃(STO), BaTiO₃ (BTO), (Bi_(x)La_(y))Ti₃O₁₂ (BLT), LaNiO₃ (LNO), YMnO₃,ZrO₂, zirconium silicate, ZrAlSiO, HfO₂, hafnium silicate, HfAlO, LaAlO,lanthanum oxide, HfO₂ doped with Si, a₂O₅, HfZrO_(x), or a combinationthereof. In some embodiments, the ferroelectric layer is referred to asa “storage layer.”

As illustrated in FIG. 4, the channel layer 400 and the source/drainregions 500 are located between the memory cell 300′ and the second gateelectrode 700. That is, the second gate electrode 700 and the memorycell 300′ are located on opposite sides of the channel layer 400. Assuch, when applying a bias to the second gate electrode 700 to turn onthe second transistor T2 (i.e. driving the electrons to pass through thechannel layer 400), the electric field generated would be far away fromthe memory cell 300′. As such, the charges stored in the memory cell300′ would not be affected by the electric field generated from applyingthe bias, thereby enhancing the read disturbance immunity. In otherwords, the stability of the storage capability of the memory cell 300′may be enhanced, and the cycle time of the memory device MD′ may beextended. Moreover, as illustrated in FIG. 4, the channel layer 400 islocated between the source/drain regions 500 and the memory cell 300′,and the source/drain regions 500 are overlapped with the first gateelectrode 200. As such, the charges stored in the memory cell 300′ caninteract/affect the electrons/charges in the channel layer 400, therebyallowing the R_(ON) of the second transistor T2 to be tunable based onthe charges stored in the memory cell 300′ and the pulse given to thefirst gate electrode 200. Since the conductance of the memory device MD′is inversely proportional to R_(ON), by modulating R_(ON) of the secondtransistor T2, the conductance of the memory device MD′ may be adjusted,thereby achieving higher flexibility in the memory device MD′.

In accordance with some embodiments of the disclosure, a memory deviceincludes a transistor and a memory cell. The transistor includes a firstgate electrode, a second gate electrode, a channel layer, and a gatedielectric layer. The second gate electrode is over the first gateelectrode. The channel layer is located between the first gate electrodeand the second gate electrode. The gate dielectric layer is locatedbetween the channel layer and the second gate electrode. The memory cellis sandwiched between the first gate electrode and the channel layer.

In accordance with some embodiments of the disclosure, an integratedcircuit includes a substrate, a first transistor, and an interconnectstructure. The first transistor is over the substrate. The interconnectstructure is disposed on the substrate. The interconnect structureincludes dielectric layers and a memory device embedded in one of thedielectric layers. The memory device includes a second transistor and amemory cell. The second transistor includes a first gate electrode, achannel layer, a second gate electrode, a gate dielectric layer, andsource/drain regions. The channel layer is over the first gateelectrode. The second gate electrode is over the channel layer. The gatedielectric layer is located between the channel layer and the secondgate electrode. The source/drain regions are located between the channellayer and the gate dielectric layer. The memory cell is sandwichedbetween the first gate electrode and the channel layer.

In accordance with some embodiments of the disclosure, a manufacturingmethod of a memory device includes at least the following steps. Adielectric layer is provided. A first gate electrode is formed on thedielectric layer. A memory cell is conformally formed on the dielectriclayer and the first gate electrode. A channel layer is deposited on thememory cell. Source/drain regions are formed on the channel layer andthe memory cell. A gate dielectric layer is deposited on thesource/drain regions and the memory cell. A second gate electrode isformed on the gate dielectric layer.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A memory device, comprising: a transistor,comprising: a first gate electrode; a second gate electrode over thefirst gate electrode; a channel layer located between the first gateelectrode and the second gate electrode; and a gate dielectric layerlocated between the channel layer and the second gate electrode; and amemory cell sandwiched between the first gate electrode and the channellayer.
 2. The memory device of claim 1, wherein the first gate electrodeis connected to a ground voltage
 3. The memory device of claim 2,wherein the second gate electrode is connected to a voltage higher thanthe ground voltage.
 4. The memory device of claim 1, wherein thetransistor further comprises: source/drain regions located between thechannel layer and the gate dielectric layer; and source/drain contactsover the gate dielectric layer, wherein the source/drain contacts areelectrically connected to the source/drain regions.
 5. The memory deviceof claim 1, wherein the channel layer comprises ZnO, IGZO, MoS₂, WS₂,WSe₂, InSe, or a combination thereof.
 6. The memory device of claim 1,wherein the gate dielectric layer comprises hexagonal boron nitride(hBN).
 7. The memory device of claim 1, wherein the memory cellcomprises: a barrier layer disposed on the first gate electrode; atunneling layer disposed over the barrier layer; and a trapping layersandwiched between the barrier layer and the tunneling layer.
 8. Thememory device of claim 1, wherein the barrier layer and the tunnelinglayer comprise aluminum oxide (AlO_(x)) or silicon oxide (SiO_(x)) andthe trapping layer comprises hafnium oxide (HfO_(x)) or silicon nitride(SiN_(x)).
 9. The memory device of claim 1, wherein the memory cellcomprises a ferroelectric layer, and the ferroelectric layer comprisesPb₃Ge₅O₁₁ (PGO), lead zirconate titanate (PZT), SrBi₂Ta₂O₉ (SBTO),SrB₄O₇ (SBO), Sr_(a)Bi_(b)Ta_(c)Nb_(d)O_(x) (SBTN), SrTiO₃ (STO), BaTiO₃(BTO), (Bi_(x)La_(y))Ti₃O₁₂ (BLT), LaNiO₃ (LNO), YMnO₃, ZrO₂, zirconiumsilicate, ZrAlSiO, HfO₂, hafnium silicate, HfAlO, LaAlO, lanthanumoxide, HfO₂ doped with Si, a₂O₅, HfZrO_(x), or a combination thereof.10. An integrated circuit, comprising: a substrate; a first transistorover the substrate; and an interconnect structure disposed on thesubstrate, comprising; dielectric layers; and a memory device embeddedin one of the dielectric layers, comprising: a second transistor,comprising: a first gate electrode; a channel layer over the first gateelectrode; a second gate electrode over the channel layer; a gatedielectric layer located between the channel layer and the second gateelectrode; and source/drain regions located between the channel layerand the gate dielectric layer; and a memory cell sandwiched between thefirst gate electrode and the channel layer.
 11. The integrated circuitof claim 10, wherein the first gate electrode and the second gateelectrode are electrically insulated.
 12. The integrated circuit ofclaim 10, wherein the channel layer comprises oxide semiconductormaterials or 2D materials.
 13. The integrated circuit of claim 10,wherein the memory cell comprises: a barrier layer disposed on the firstgate electrode; a tunneling layer disposed over the barrier layer; and atrapping layer sandwiched between the barrier layer and the tunnelinglayer.
 14. The integrated circuit of claim 13, wherein a material of thebarrier layer and a material of the tunneling layer are the same, andthe material of the barrier layer and a material of the trapping layerare different.
 15. The integrated circuit of claim 10, wherein thememory cell comprises a ferroelectric layer.
 16. The integrated circuitof claim 10, wherein the source/drain regions are in physical contactwith the channel layer and the memory cell.
 17. The integrated circuitof claim 10, wherein gate dielectric layer is in physical contact withthe source/drain regions and the memory cell.
 18. A manufacturing methodof a memory device, comprising: providing a dielectric layer; forming afirst gate electrode on the dielectric layer; conformally forming amemory cell on the dielectric layer and the first gate electrode;depositing a channel layer on the memory cell; forming source/drainregions on the channel layer and the memory cell; depositing a gatedielectric layer on the source/drain regions and the memory cell; andforming a second gate electrode on the gate dielectric layer.
 19. Themethod of claim 18, wherein forming the memory cell comprises:depositing a barrier layer on the dielectric layer and the first gateelectrode; depositing a trapping layer on the barrier layer; anddepositing a tunneling layer on the trapping layer, wherein a materialof the barrier layer and a material of the tunneling layer are the same,and the material of the barrier layer and a material of the trappinglayer are different.
 20. The method of claim 18, further comprising:forming openings in the gate dielectric layer to expose at least aportion of the source/drain regions; and forming source/drain contactsover the gate dielectric layer, wherein the source/drain contacts extendinto the openings to be in physical contact with the source/drainregions.